In power semiconductor devices, achieving the highest breakdown voltage simultaneously with minimal on-resistance is one of the most important performance characteristics. Lateral geometry devices, such as field-effect transistors (FETs), including metal oxide semiconductor FETs (MOSFETs), metal semiconductor FETs (MESFETs), high electron mobility transistors (HEMTs), etc., have a channel aligned along the semiconductor surface, and which is often located close to the semiconductor surface. If the space-charge (depletion) region occupies only a portion of the gate-drain spacing, the electric field in that spacing is strongly non-uniform and can result in premature breakdown, which limits the device performance. Due to a high carrier concentration in the channel and the close vicinity of the channel to the semiconductor surface, efficient control over the space charge distribution in the gate-drain spacing is extremely challenging. This problem is particularly important in wide bandgap devices with high electron density in the channel and polarization charges induced at heterointerfaces, which impede channel depletion over a large gate-drain spacing.
One approach to lower the peak electric field near the gate edge is the use of one or more field-modulating plates (FPs), which can be connected to either the gate, source, or drain electrode. FIG. 1 shows a conventional heterostructure FET (HFET) 2 including a field plate FP according to the prior art. The field plate structure decreases the peak field near the gate electrode edge by splitting it into two peaks, thereby increasing the breakdown voltage for the device.
However, even multiple field plate structures, which split the electric field into even more peaks, cannot achieve a uniform electric field in the device channel. Additionally, a device including field plate(s) can suffer from premature breakdown between the field plate(s) and the drain electrode. Furthermore, the field plate(s) increases the inter-electrode and electrode-semiconductor capacitances and therefore decreases the device maximum operating frequency.
As a result of the above limitations, current high-voltage FET switches including field plates do not achieve the breakdown voltages predicted by fundamental material properties and have on-resistances higher than that expected from the material properties.
Another approach proposes a device that combines a lateral source-gate region and a vertical (perpendicular to the device surface) gate-drain drift region. FIG. 2 shows an illustrative lateral/vertical device 4 according to the prior art. Such devices 4 have been fabricated in silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and other material systems. These devices 4 include buried p-doped layers (e.g., p-GaN shown in FIG. 2) for high voltage blocking, isolation, and current control.
However, inclusion of buried p-doped layers can have drawbacks. For example, formation of the p-doped islands buried in n-type material can be difficult. Furthermore, inclusion of the p-doped layers can form parasitic n-p-n transistors, which can lead to excessive leakage and premature breakdown. For devices 4 fabricated using materials from the group III-nitride material system, the combined lateral/vertical approach with buried p-doped layers does not apply well. For example, while group III-nitride based devices offer tremendous performance improvement due to a high breakdown field and other unique material properties, including buried p-doped group III-nitride layers leads to significant degradation of material properties and considerable complications to the growth/fabrication technology, which prevents cost reduction.